The present invention relates to comparison circuits suitable for fabrication in integrated circuit form and more particularly to a comparison circuit for triggering an output pulse delayed in time in response to an applied input signal obtaining a predetermined level state.
In many types of electronic systems there is a need for a comparison circuit for producing an output signal in response to an applied input signal being of a predetermined level with respect to a reference potential. An example of the need for such a comparison circuit is a Secam television chroma demodulator system wherein the chroma information is restructured in the television receiver from two successive lines of transmitted image. In such television chroma demodulators, a line by line switch must be synchronized with the Secam signal in the correct phase to permit the foregoing. A widely used technique employs a binary divider switched by a pulse at the start of each line and set to the correct phase by an identification circuit. To obtain the correct phasing the identification circuit integrates successive identification signals provided in the received Secam signal over a period of many television lines and if the phasing is incorrect a trigger circuit is utilized for producing an identification correcting pulse for correcting the output from the binary divider.
One problem with some prior art identification circuits arise with the need to integrate the information signals over a period of many lines in order to obtain satisfactory performance with poor signal to noise ratios. Due to the extended time required for integration of the identification signals the identification correcting pulse sometimes corresponds with the divider switching period and is thus ineffective. As a result, two or more attempts at identification may be necessary in some prior art circuits.
Hence, there is a need for a comparison circuit which can produce a correction signal which can never correspond with the normal switching period of the binary divider.